UGC NET CS Practice Set 2

Explanation: A 2ⁿ-to-1 MUX has n select lines and can directly implement any function of n variables. However, by using one additional variable at the data inputs (0, 1, X, X'), a 4-to-1 MUX (2 select lines) can implement any function of 3 variables.

Explanation: A mod-N counter needs ⌈log₂(N)⌉ flip-flops. For mod-10: ⌈log₂(10)⌉ = ⌈3.32⌉ = 4 flip-flops. These 4 flip-flops can represent states 0000 to 1001 (0 to 9).

Explanation: Ideal CPI in a pipeline is 1. Branch frequency = 1/5 = 0.2. Penalty = 3 cycles. Effective CPI = 1 + (branch frequency × penalty) = 1 + (0.2 × 3) = 1 + 0.6 = 1.6.

Explanation: In a direct-mapped cache, memory address bits = tag bits + index bits. Index bits = log₂(256) = 8. Total memory address bits = log₂(64K) = 16. Tag bits = 16 − 8 = 8.

Explanation: Virtual memory allows a process's logical address space to exceed physical memory by keeping only needed pages/segments in RAM and the rest on disk. This enables running programs larger than available physical memory.

Explanation: In n-bit 2's complement, the range is −2^(n−1) to 2^(n−1)−1. For 8 bits: −2^7 to 2^7−1 = −128 to +127. There are 256 values total with one more negative number than positive.

Explanation: Offset bits = log₂(64) = 6. Index bits = log₂(128) = 7. Tag bits = 32 − 6 − 7 = 19. The number of blocks per set (associativity) does not affect the address decomposition.

Explanation: IEEE 754 single precision uses 8 bits for the exponent with a bias of 2^(8−1) − 1 = 127. The stored exponent = actual exponent + 127. (1023 is the bias for double precision with 11-bit exponent.)

Explanation: Non-pipelined execution takes 6 cycles per instruction. Pipelined CPI = 1 + 0.3 × 1 = 1.3. Speedup = 6 / 1.3 ≈ 4.62. Without hazards, the ideal speedup would be 6.

Explanation: A load-use hazard cannot be fully resolved by forwarding alone. The load instruction produces its result at the end of the MEM stage, but the dependent instruction needs it at the beginning of EX. One stall cycle is still needed even with forwarding.

Explanation: RISC (Reduced Instruction Set Computer) features include fixed-length instructions, load-store architecture (only load/store access memory), large register files, hardwired control unit, and simple addressing modes.

Explanation: Effective time = L1 time + (L1 miss rate × L2 time) + (L1 miss rate × L2 miss rate × Memory time) = 1 + 0.05×10 + 0.05×0.20×100 = 1 + 0.5 + 1.0 = 2.5 ns.

Explanation: A microinstruction in a microprogrammed control unit contains control fields that generate control signals for the datapath components and a next-address field that determines the next microinstruction to execute.

Explanation: DMA allows I/O devices to transfer blocks of data directly to/from main memory without requiring the CPU for each word transfer. The CPU initiates the transfer and is interrupted when it completes, freeing it for other work.

Explanation: F = AB + CD. Converting to NAND: F = ((AB)'·(CD)')'. Gate 1: NAND(A,B) = (AB)'. Gate 2: NAND(C,D) = (CD)'. Gate 3: NAND(Gate1, Gate2) = ((AB)'·(CD)')' = AB + CD. Wait, that's only 3. But NAND(NAND(A,B), NAND(C,D)) = (((AB)'(CD)'))' = AB+CD by De Morgan. So actually 3 NAND gates suffice. Hmm — but the answer typically accounts for the AND-OR pattern needing inversions. Actually F = ((AB)''·(CD)'')' cannot be simplified this way. Using the two-level NAND-NAND: F = ((AB)'·(CD)')' requires 3 gates. The answer is 3.

Explanation: 3 in binary is 00000011. Booth's encoding looks at bit pairs (current, previous): scanning right to left gives transitions. For 011(0): bit0=1,prev=0 → subtract; bit1=1,prev=1 → no op; bit2=0,prev=1 → add. So 2 operations (one subtract, one add). Booth's algorithm reduces the number of operations by encoding runs of 1s.

Explanation: When a branch is fetched in IF, the next two instructions are fetched before the branch is resolved at the end of EX. If the branch is taken, these 2 instructions must be flushed. The penalty is 2 cycles (the number of stages between IF and the resolution stage EX).

Explanation: Page offset = log₂(4 KB) = log₂(4096) = 12 bits. Number of pages = 2^(32−12) = 2^20 = 1,048,576. Each page needs one page table entry.

Explanation: Register-to-register operations only (load-store architecture) is a RISC characteristic. CISC supports memory-to-register and memory-to-memory operations. CISC features include variable-length instructions, many addressing modes, and microprogrammed control.

Explanation: In C, modifying a variable more than once between two sequence points is undefined behavior. The expression x++ + ++x modifies x twice without an intervening sequence point, so the result is undefined by the C standard.

Explanation: Call by reference passes the address (reference) of the actual parameter. Any changes to the formal parameter directly affect the actual parameter. Call by value copies the value, call by name uses textual substitution, and call by value-result copies in and copies back.

Explanation: The Liskov Substitution Principle (LSP), one of the SOLID principles, states that objects of a superclass should be replaceable with objects of its subclasses without affecting the correctness of the program.

Explanation: To rotate about an arbitrary point (h,k): first translate the point to the origin T(−h,−k), then apply the rotation R(θ), then translate back T(h,k). The composite transformation is T(h,k) · R(θ) · T(−h,−k).

Explanation: The Cohen-Sutherland algorithm divides the plane into 9 regions using a 4-bit code (TBRL — Top, Bottom, Right, Left). Each bit indicates whether the endpoint is above, below, to the right, or to the left of the clipping window.

Explanation: Parallel (orthographic) projection preserves parallel lines because all projectors are parallel to each other. Perspective projections cause parallel lines to converge at vanishing points.

Explanation: The Z-buffer algorithm processes each polygon and for each polygon, rasterizes it pixel by pixel, comparing depth values. The complexity is O(n×p) in the worst case, where n is the number of polygons and p is the number of pixels each polygon covers.

Explanation: Bresenham's line algorithm uses only integer arithmetic (addition, subtraction, and bit shifting), making it very efficient for rasterization. It avoids the floating-point multiplication and rounding required by the DDA algorithm.

Explanation: The map function applies the given function (squaring, in this case) to each element of the list. map (\x -> x*x) [1,2,3,4] = [1*1, 2*2, 3*3, 4*4] = [1, 4, 9, 16].

Explanation: The Sutherland-Hodgman algorithm clips a polygon against each edge of the clip window one at a time, in sequence. The output of clipping against one edge becomes the input for clipping against the next edge.

Explanation: Java is considered type-safe because it enforces type checking at both compile time and runtime, prevents arbitrary pointer arithmetic, and does not allow implicit unsafe type casts. C and C++ allow pointer arithmetic and unchecked casts, making them not type-safe.