UGC NET CS Practice Set 9

Explanation: Peephole optimization examines a small, fixed-size window (peephole) of consecutive instructions and replaces inefficient patterns with more efficient ones. Examples: redundant load/store elimination, strength reduction (multiply by 2 → shift left), removing unreachable code.

Explanation: NAT primarily operates at the Network Layer (modifying IP addresses) and also at the Transport Layer when performing port address translation (PAT/NAPT — modifying port numbers). It enables multiple devices on a private network to share a single public IP address.

Explanation: Crossover (recombination) combines genetic material from two parent chromosomes to create offspring. Common types include single-point crossover (swap tails at a random point), two-point crossover, and uniform crossover. Randomly changing bits is mutation, not crossover.

Explanation: There are 11 non-isomorphic simple graphs on 4 vertices: the empty graph (0 edges), 1 edge, a path P₂ (2 edges), a triangle, a matching (2 independent edges), P₃ (3 edges path), star K₁₃, C₄, K₄−e (diamond), K₄ minus a matching, and K₄. Total = 11.

Explanation: Availability = MTBF / (MTBF + MTTR), where MTBF is Mean Time Between Failures and MTTR is Mean Time To Repair. High availability requires high MTBF (few failures) and low MTTR (quick repairs). E.g., MTBF=990h, MTTR=10h → Availability = 990/1000 = 99%.

Explanation: S ⇒ aAB ⇒ abBcB ⇒ abdcB ⇒ abdcε = abdc. The last B derives ε (the empty string), producing the terminal string 'abdc'. This is a valid leftmost derivation.

Explanation: Data independence means the ability to modify the schema at one level without affecting the schema at the next higher level. Physical data independence: change storage/access methods without changing the logical schema. Logical data independence: change the logical schema without changing external schemas/apps.

Explanation: An activation record contains local variables, parameters, return address, saved registers, dynamic link (to caller's frame), and static link (for nested scopes). The global symbol table is a compile-time structure maintained separately, not part of individual activation records.

Explanation: IPv6 uses 128-bit addresses (vs IPv4's 32-bit), providing 2^128 ≈ 3.4 × 10^38 unique addresses. IPv6 addresses are written as eight groups of four hexadecimal digits (e.g., 2001:0db8:85a3:0000:0000:8a2e:0370:7334).

Explanation: Hamming distance is the number of positions where the corresponding bits differ. XOR: 10110101 ⊕ 10011010 = 00101111. Number of 1s in the XOR = 5. So the Hamming distance is 5.

Explanation: CRC with a well-chosen generator polynomial of degree r can detect: all single-bit errors, all double-bit errors (if the polynomial has at least 3 terms), all odd-number-of-bit errors (if (x+1) is a factor), and all burst errors of length ≤ r.

Explanation: Dead code elimination removes code that computes values never used by the program (dead variables) and code that is unreachable (e.g., code after an unconditional return/goto). This reduces code size and may improve cache performance.

Explanation: The Cartesian product R × S pairs every tuple in R with every tuple in S. Result has |R| × |S| = 5 × 3 = 15 tuples and deg(R) + deg(S) = 2 + 2 = 4 attributes (A, B, C, D).

Explanation: A context switch involves saving the CPU state (registers, program counter, stack pointer, etc.) of the currently running process into its PCB, and loading the saved state of the next process to run. This is pure overhead and modern CPUs optimize it but cannot eliminate it.

Explanation: The carry ripples through 4 stages: 3 carry delays through the first 3 adders = 3 × 2 = 6, then the final sum output delay = 3, plus the initial carry delay from the first adder = 2. Total = 2 + 2 + 2 + 3 = 9. Actually: C1 ready at 2, C2 at 4, C3 at 6, C4 at 8. S4 = 6 + 3 = 9. Wait, the worst case: carry propagates through all 4 FAs (3 × 2 = 6 for C1..C3), then the last FA sum needs the carry at time 6 plus 3 = 9. But if the first FA carry is at 2, then C2 at 4, C3 at 6, S4 = 6 + 3 = 9. The carry chain is 3 intermediate carries × 2 = 6 delays for carry plus last sum = 3, giving 6 + 3 + 2 = 11 (counting from input to C0 output at 2).

Explanation: When J=K=1, the JK flip-flop toggles its output on each clock edge — if Q was 0, it becomes 1, and vice versa. This is the toggle mode. J=1,K=0 sets; J=0,K=1 resets; J=0,K=0 holds.

Explanation: A CLA computes generate Gᵢ = Aᵢ·Bᵢ and propagate Pᵢ = Aᵢ⊕Bᵢ for each bit position in parallel. Then carries are computed: C₁ = G₀ + P₀·C₀, C₂ = G₁ + P₁·G₀ + P₁·P₀·C₀, etc. This eliminates the ripple delay.

Explanation: In immediate addressing mode, the operand value is embedded directly in the instruction (e.g., MOV R1, #5). Direct mode gives a memory address, register mode names a register, and indirect mode gives the address of a location holding the target address.

Explanation: In a set-associative cache, the index bits determine the set. Within the set (which has 2 blocks in 2-way), a replacement policy like LRU, FIFO, or random selects which block to evict on a miss.

Explanation: Booth's recoding appends a 0 to the right: 0110_0. Scanning pairs from right: bit0=0,prev=0→0; bit1=1,prev=0→−1; bit2=1,prev=1→0; bit3=0,prev=1→+1. So the operations are: subtract at position 1, add at position 3: 0110 = 1000 − 0010 = 8 − 2 = 6. Only 2 operations instead of 2 additions.

Explanation: The TLB is a small, fast, fully-associative cache that stores recent virtual-to-physical page number translations. Without a TLB, every memory access would require one or more page table lookups in main memory, significantly slowing execution.

Explanation: Amdahl's Law: Speedup = 1 / (S + (1−S)/N), where S is the serial fraction and N is the number of processors. As N→∞, speedup → 1/S. If 10% of the program is serial (S=0.1), maximum speedup is 10× regardless of processor count.

Explanation: When an interrupt is asserted, the CPU completes the current instruction, saves its state (PC, flags, registers) on the stack, and jumps to the interrupt service routine (ISR) via the interrupt vector table. After the ISR completes, the saved state is restored.

Explanation: Harvard architecture has separate instruction and data memories (and buses), allowing simultaneous access to both. Von Neumann uses a single memory for both, creating a bottleneck. Harvard is common in DSPs and microcontrollers; modified Harvard (shared L2 cache) is used in modern CPUs.

Explanation: Write-through updates main memory on every cache write (simple, consistent but slow). Write-back updates main memory only when the dirty cache line is evicted (faster but more complex). Write-back requires a dirty bit per cache line.

Explanation: Lazy evaluation (used in Haskell) delays evaluation of an expression until its value is required. This enables working with infinite data structures, avoids unnecessary computation, but can make space usage harder to predict. Strict/eager evaluation (C, Java) evaluates immediately.

Explanation: Runtime (dynamic) polymorphism in C++ uses virtual functions. The correct function is determined at runtime via the vtable (virtual table). Function overloading and operator overloading are compile-time (static) polymorphism. Templates are also resolved at compile time.

Explanation: Phong shading interpolates the normal vectors across the polygon surface and computes the illumination model at each pixel, producing more accurate highlights than Gouraud shading (which interpolates colors). Phong is more computationally expensive but gives better specular highlights.

Explanation: In homogeneous coordinates, a 2D point (x, y) is represented as (x, y, 1) or more generally (wx, wy, w) for any w ≠ 0. This allows translation to be represented as matrix multiplication, unifying all 2D transformations into 3×3 matrices.

Explanation: Standard projections include parallel projections (orthographic: front/top/side, axonometric: isometric/dimetric/trimetric) and oblique (cavalier, cabinet). Perspective projections have 1, 2, or 3 vanishing points. Hyperbolic projection is not a standard computer graphics projection type.